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? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan3111 ? rev. 1.0.2 januar y 2011 fan3111 ? single 1a high-speed, low-side gate driver fan3111 ? single 1a high-speed, low-side gate driver features ? 1.4a peak sink / source at v dd = 12v ? 1.1a sink / 0.9a source at v out = 6v ? 4.5 to 18v operating range ? fan3111c compatible with FAN3100C footprint ? two input configurations: ? dual cmos inputs allow configuration as non-inverting or inverting with enable function ? single non-inverting, low-voltage input for compatibility with low-voltage controllers ? small footprint facilitates distributed drivers for parallel power devices ? 15ns typical delay times ? 9ns typical rise / 8ns typical fall times with 470pf load ? 5-pin sot23 package ? rated from ?40c to 125c ambient applications ? switch-mode power supplies ? synchronous rectifier circuits ? pulse transformer driver ? logic to power buffer ? motor control description the fan3111 1a gate driver is designed to drive an n- channel enhancement-mode mosfet in low-side switching applications. two input options are offered: fan3111c has dual cmos inputs with thresholds referenced to v dd for use with pwm controllers and other input-signal sources that operate from the same supply voltage as the driver. for use with low-voltage contro llers and other input-signal sources that operate from a lower supply voltage than the driver, that supply volt age may also be used as the reference for the input thresholds of the fan3111e. this driver has a single, non- inverting, low-voltage input plus a dc input v xref for an external reference voltage in the range 2 to 5v. the fan3111 is available in a lead-free finish industry- standard 5-pin sot23. figure 1. fan3111c (top view) figure 2. fan3111e (top view)
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan3111 ? rev. 1.0.2 2 fan3111 ? single 1a high-speed, low-side gate driver ordering information part number input threshold package packing method quantity per reel fan3111csx cmos 5-pin sot23 tape & reel 3,000 fan3111esx external 5-pin sot23 tape & reel 3,000 thermal characteristics (1) package ? jl (2) ? jt (3) ? ja (4) ? jb (5) ? jt (6) units 5-pin sot23 58 102 161 53 6 c/w notes: 1. estimates derived from thermal simulati on; actual values depend on the application. 2. theta_jl ( ? jl ): thermal resistance between the semiconductor j unction and the bottom surface of all the leads (including any thermal pad) that ar e typically soldered to a pcb. 3. theta_jt ( ? jt ): thermal resistance between the semiconductor junction and the top surf ace of the package, assuming it is held at a uniform te mperature by a top-side heatsink. 4. theta_ja ( ja ): thermal resistance between junction and ambi ent, dependent on the pcb design, heat sinking, and airflow. the value given is for natural convection with no heatsink using a 2s2p board,, as specified in jedec standards jesd51-2, jesd51- 5, and jesd51-7, as appropriate. 5. psi_jb ( ? jb ): thermal characterization parameter prov iding correlation between semiconductor junction temperature and an application circuit boar d reference point for the thermal environment defined in note 4. for the mlp-8 package, the board refer ence is defined as the pcb copper connected to the thermal pad and protruding from either end of the package. for the soic-8 package, t he board reference is defined as the pcb copper adjacent to pin 6. 6. psi_jt ( ? jt ): thermal characterization parameter provid ing correlation between the semiconductor junction temperature and the center of the top of the pack age for the thermal environm ent defined in note 4. pin definitions pin # name description 1 vdd supply voltage . provides power to the ic. 2 gnd ground . common ground reference for input and output circuits. 3 in+ non-inverting input . connect to vdd to enable output. 4 in? fan3111c inverting input . connect to gnd to enable output. xref fan3111e external reference voltage . reference for input thresholds, 2v to 5v. 5 out gate drive output . held low unless required inputs are present. output logic with dual-input configuration in+ in ? out 0 (7) 0 0 0 (7) 1 (7) 0 1 0 1 1 1 (7) 0 note: 7. default input signal if no external connection is made.
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan3111 ? rev. 1.0.2 3 fan3111 ? single 1a high-speed, low-side gate driver block diagrams 1 vdd 5 out 2 gnd in+ 3 4 v dd 100k ? 100k ? 100k ? in- figure 3. fan3111c simplified block diagram 1 vdd 5 out 2 gnd in+ 3 4 100k ? 100k ? xref figure 4. fan3111e simplified block diagram
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan3111 ? rev. 1.0.2 4 fan3111 ? single 1a high-speed, low-side gate driver absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the devic e may not function or be operable above the recommended operating c onditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stre sses above the recommended operating conditi ons may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter min. max. uni t v dd vdd to gnd -0.3 20.0 v v in voltage on in to gnd fan3111c -0.3 v dd + 0.3 v fan3111e -0.3 v xref +0.3 v v xref voltage on xref to gnd fan3111e -0.3 5.5 v v out voltage on out to gnd -0.3 v dd +0.3 v t l lead soldering temperature (10 seconds) +260 oc t j junction temperature +150 oc t stg storage temperature -65 +150 oc esd human body model, jesd22-a114 2000 v charged device model, jesd22-c101 2500 recommended operating conditions the recommended operating conditions table defines the conditions for actual device oper ation. recommended operating conditions are specified to ens ure optimal performance to the datasheet specificat ions. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter min. max. unit v dd supply voltage range 4.5 18.0 v v in input voltage in fan3111c 0 v dd v fan3111e 0 v xref v v xref external reference voltage xref fan3111e 2.0 5.0 v t a operating ambient te mperature -40 +125 oc
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan3111 ? rev. 1.0.2 5 fan3111 ? single 1a high-speed, low-side gate driver electrical characteristics unless otherwise noted, v dd = 12v, v xref = 3.3v, t j = -40c to +125c. currents ar e defined as positive into the device and negative out of the device. symbol parameter conditions min. typ. max. unit supply v dd operating range 4.5 18.0 v i dd static supply current i nputs not connected 5 10 a inputs (fan3111c) v il_c in logic, low-voltage threshold 30 38 %v dd v ih_c in logic, high-voltage threshold 55 70 %v dd i inl in current, low in from 0 to v dd -1 175 a i inh in current, high in from 0 to v dd -175 1 a v hys_c input hysteresis voltage 17 %v dd inputs (fan3111e) v il_e in logic, low-voltage threshold 25 30 %v xref v ih_e in logic, high-voltage threshold 50 60 %v xref i inl in current, low in from 0 to v xref -1 50 a i inh in current, high in from 0 to v xref -50 1 a v hys_e input hysteresis voltage 20 %v xref output i sink out current, mid-voltage, sinking (8) out at v dd /2, c load = 47nf, f = 1khz 1.1 a i source out current, mid-voltage, sourcing (8) out at v dd /2, c load = 47nf, f = 1khz -0.9 a i pk_sink out current, peak, sinking (8) c load = 47nf, f = 1khz 1.4 a i pk_source out current, peak, sourcing (8) c load = 47nf, f = 1khz -1.4 a t rise output rise time (9) c load = 470pf 9 18 ns t fall output fall time (9) c load = 470pf 8 17 ns t d1 , t d2 output prop. delay (9) fan3111c : 0 - 12v in , 1v/ns slew rate 15 30 ns fan3111e : 0 - 3.3v in , 1v/ns slew rate i rvs output reverse current withstand (8) 250 ma notes: 8. not tested in production. 9. see timing diagrams .
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan3111 ? rev. 1.0.2 6 fan3111 ? single 1a high-speed, low-side gate driver timing diagrams 90% 10% output in+ t d1 t d2 t rise t fall v inl v inh 90% 10% output t d1 t d2 t fall t rise v inl v inh in - figure 5. non-inverting waveforms figure 6. inverting waveforms
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan3111 ? rev. 1.0.2 7 fan3111 ? single 1a high-speed, low-side gate driver typical performance characteristics typical characteristics are provided at 25c, v dd = 12v, and v xref = 3.3v unless otherwise noted. 0.0 0.5 1.0 1.5 2.0 2.5 4 6 8 1012141618 supply voltage (v) i dd ( a) fan3 1 1 1 c inputs floating, output low 0.0 0.5 1.0 1.5 2.0 2.5 4 6 8 1012141618 supply voltage (v) i dd ( a) fan3 1 1 1 e inputs floating, output low figure 7. i dd (static) vs. supply voltage figure 8. i dd (static) vs. supply voltage 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0 200 400 600 800 1000 sw itching frequency (khz) i dd (ma) fan3 1 1 1 c 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0 200 400 600 800 1000 sw itching frequency (khz) i dd (ma) v dd = 15v v dd = 12v v dd =8v v dd =4.5v fan3111c 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0 200 400 600 800 1000 sw itching frequency (khz) i dd (ma) fan3111e v dd = 15v v dd =12v v dd =8v v dd =4.5v figure 9. i dd (no-load) vs. frequency figure 10. i dd (no-load) vs. frequency 0 1 2 3 4 5 6 7 8 9 0 200 400 600 800 1000 sw itchin g fr e q uenc y ( khz ) i dd (ma) fan3111c v dd =15v v dd =12v v dd =8v v dd = 4.5v 0 1 2 3 4 5 6 7 8 9 0 200 400 600 800 1000 sw itchin g fr e q uenc y ( khz ) i dd (ma) fan3111e v dd =15v v dd =12v v dd =8v v dd =4.5v figure 11. i dd (470pf load) vs. frequency figure 12. i dd (470pf load) vs. frequency
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan3111 ? rev. 1.0.2 8 fan3111 ? single 1a high-speed, low-side gate driver typical performance characteristics typical characteristics are provided at 25c, v dd = 12v, and v xref = 3.3v unless otherwise noted. 0 1 2 3 -50 -25 0 25 50 75 100 125 tem p erature ( c ) i dd ( a) fan3111c inputs floating, output low 0 1 2 3 -50 -25 0 25 50 75 100 125 temperature (c) i dd ( a) fan3 1 1 1 e inputs floating, output low figure 13. i dd (static) vs. temperature figure 14. i dd (static) vs. temperature 0 1 2 3 4 5 6 7 8 9 10 4 6 8 10121416 18 supply voltage (v) input thresholds (v) fan3111c v il v ih 0.5 1.0 1.5 2.0 2.5 2.5 3.0 3.5 4.0 4.5 5.0 xref (v) input thresholds (v) fan3 1 1 1 e v ih v i l figure 15. input thresholds vs. supply voltage figure 16. input threshold vs. xref voltage 0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% 4 6 8 1012141618 supply voltage (v) input thresholds (% of v dd ) fan3111c v il v ih 4.0 4.5 5.0 5.5 6.0 6.5 7.0 -50 -25 0 25 50 75 100 125 temperature (c) input thresholds (v) f a n3111c v il v ih figure 17. input thresholds % vs. supply voltag e figure 18. input threshold vs. temperature
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan3111 ? rev. 1.0.2 9 fan3111 ? single 1a high-speed, low-side gate driver typical performance characteristics typical characteristics are provided at 25c, v dd = 12v, and v xref = 3.3v unless otherwise noted. 0.8 1.0 1.2 1.4 1.6 1.8 2.0 -50 -25 0 25 50 75 100 125 temperature (c) input thresholds (v) fan3111e v i l v ih 0 10 20 30 40 50 60 70 4 6 8 1012141618 supply voltage (v) propagation delays (ns) in rise to out fall in fall to out fan3111c inverting input figure 19. input threshold vs. temperature figure 20. propagation delay vs. supply voltage 0 10 20 30 40 50 60 70 80 4 6 8 10 12141618 supply voltage (v) propagation delays (ns) fan3111c non-inverting input in fall to out fall in ri s e t o o u tri s e 0 10 20 30 40 50 60 70 80 90 4 6 8 1012141618 supply voltage (v) propagation delays (ns) fan3 1 1 1 e in fall to out fall in rise to out rise figure 21. propagation delay vs. supply voltage figure 22. propagation delay vs. supply voltage 10 12 14 16 18 20 22 24 -50 -25 0 25 50 75 100 125 temperature (c) propagation delays (ns) in f all to out f all in rise to out rise fan3111c non-inverting input 8 10 12 14 16 18 20 -50 -25 0 25 50 75 100 125 temperature (c) propagation delays (ns) in fall to out fall in r is e to out r is e fan3111e figure 23. propagation delay vs. temperature figure 24. propagation delays vs. temperature
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan3111 ? rev. 1.0.2 10 fan3111 ? single 1a high-speed, low-side gate driver typical performance characteristics typical characteristics are provided at 25c, v dd = 12v, and v xref = 3.3v unless otherwise noted. 10 12 14 16 18 20 22 -50 -25 0 25 50 75 100 125 temperature (c) propagation delays (ns) in rise to out fall in f all to out r is e fan3111c inverting input 0 20 40 60 80 100 120 0 5 10 15 20 supply voltage (v) fall time (ns) c l =4.7nf c l =2.2nf c l =1.0nf c l =470pf figure 25. propagation delays vs. temperature figure 26. fall time vs. supply voltage 0 20 40 60 80 100 120 140 0 5 10 15 2 0 su pp l y v olta g e ( v ) rise time (ns) c l =4.7nf c l =2.2nf c l =1.0nf c l =470pf 7 8 9 10 11 12 -50 -25 0 25 50 75 100 125 temperature (c) rise and fall times (ns) r ise tim e fall tim e c l =470pf figure 27. rise time vs. supply voltage figure 28. rise and fall time vs. temperature figure 29. rise and fall waveforms (470pf) figure 30. quasi-static source current (v dd =12v)
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan3111 ? rev. 1.0.2 11 fan3111 ? single 1a high-speed, low-side gate driver typical performance characteristics typical characteristics are provided at 25c, v dd = 12v, and v xref = 3.3v unless otherwise noted. figure 31. quasi-static sink current (v dd =12v) figure 32. quasi-static source current (v dd =8v) 470f al. el. v dd v out 1f ceramic 4.7f ceramic c load 47nf i out in 1khz current probe lecroy ap015 fan3111 figure 33. quasi-static sink current (v dd =8v) figure 34. quasi-static i out / v out test circuit
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan3111 ? rev. 1.0.2 12 fan3111 ? single 1a high-speed, low-side gate driver applications information the fan3111 offers cmos- or logic-level-compatible input thresholds. in the fan3111c, the logic input thresholds are dependent on the v dd level and, with v dd of 12v, the logic rising-edge threshold is approximately 55% of v dd and the input falling-edge threshold is approximately 38% of v dd . the cmos input configuration offers a hysteresis voltage of approximately 17% of v dd . the cmos inputs can be used with relatively slow edges (approaching dc) if good decoupling and bypass techniques are incorporated in the system des ign to prevent noise from violating the input-voltage hysteresis window. this allows setting precise timing intervals by fitting an r-c circuit between the controlli ng signal and the in pin of the driver. the slow rising edge at the in pin of the driver introduces a delay between the controlling signal and the out pin of the driver. in the fan3111e, the input thresholds are dependent on the v xref voltage that typically is chosen between 2v and 5v. this range of v xref allows compatibility with ttl and other logic levels up to 5v by connecting the xref pin to the same source as the logic circuit that drives the fan3111e input stage. the logic rising edge threshold is approximately 50% of v xref and the input falling-edge threshold is approximately 30% of v xref . the ttl-like input configurat ion offers a hysteresis voltage of approximately 20% of v xref . startup operation the fan3111 internal logic is optimized to drive ground referenced n-channel mosfets as v dd supply voltage rises during start up operation. as v dd rises from 0v to approximately 2v, the out pin is held low by an internal resistor, regardless of the state of the input pins. when the internal circuitry becomes active at approximately 2v, the out put assumes the state commanded by the inputs. figure 35 illustrates fan3111c startup operation with v dd increasing from 0 to 12v, with the output commanded to the low level (in+ and in- tied to ground). note that out is held low to maintain an n- channel mosfet in the off state. out @ 5 v/div vdd @ 5 v/div t = 200 us/div vdd out fan3111c figure 35. fan3111c startup operation figure 36 illustrates st artup operation as v dd increases from 0 to 12v with the output commanded to the high level (in+ tied to vdd, in- tied to gnd). this configuration might not be su itable for driving high-side p-channel mosfets because t he low output voltage of the driver would attempt to turn the p-channel mosfet on with low v dd levels. out @ 5 v/div vdd @ 5 v/div vdd out fan3111c t = 200 us/div figure 36. startup operation as v dd increases figure 37 illustrates fan3111e startup operation with the output commanded to the low level (in+ tied to ground) and the voltage on xref ramped from 0 to 3.3v. t = 50 us/div out @ 2 v/div vxref @ 2 v/div vdd @ 5 v/div vdd out fan3111e xref figure 37. fan3111e startup operation millerdrive? gate drive technology fan3111 drivers incorporate t he millerdrive architecture shown in figure 38 for the output stage, a combination of bipolar and mos devices capable of providing large currents over a wide r ange of supply-voltage and temperature variations. the bipolar devices carry the bulk of the current as out swings between 1/3 to 2/3 v dd and the mos devices pull t he output to the high or low rail. the purpose of the millerdrive architecture is to speed up switching by providing t he highest current during the miller plateau region when the gate-drain capacitance of the mosfet is being charged or discharged as part of the turn-on / turn-off process. for applications with zero voltage switching during the mosfet turn-on or turn-off interval, the driver supplies high peak current for fast switching even though the mille r plateau is not present. this situation often occurs in synchronous rectifier applications because the body diode is generally conducting before the mosf et is switched on.
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan3111 ? rev. 1.0.2 13 fan3111 ? single 1a high-speed, low-side gate driver the output-pin slew rate is determined by v dd voltage and the load on the output. it is not user adjustable, but if a slower rise or fall ti me at the mosfet gate is needed, a series resistor can be added. figure 38. millerdrive? output architecture v dd bypass capacitor guidelines to enable this ic to turn a power device on quickly, a local, high-frequency, bypass capacitor c byp with low esr and esl should be connected between the vdd and gnd pins with minimal tr ace length. this capacitor is in addition to bulk electrolytic capacitance of 10f to 47f often found on driver and controller bias circuits. a typical criterion for choosing the value of c byp is to keep the ripple voltage on the v dd supply 5%. often this is achieved with a value 20 times the equivalent load capacitance c eqv , defined here as q gate /v dd . ceramic capacitors of 0.1f to 1f or larger are common choices, as are dielectrics, such as x5r and x7r, which have good temper ature characteristics and high pulse current capability. if circuit noise affects normal operation, the value of c byp may be increased to 50-100 times the c eqv or c byp may be split into two capacit ors. one should be a larger value, based on equivalent load capacitance, and the other a smaller value, such as 1-10nf, mounted closest to the vdd and gnd pins to carry the higher-frequency components of the current pulses. layout and connection guidelines the fan3111 incorporates fast reacting input circuits, short propagation delays, and output stages capable of delivering current peaks over 1a to facilitate voltage transition times from under 10ns to over 100ns. the following layout and connection guidelines are strongly recommended: ? keep high-current output and power ground paths separate from logic input signals and signal ground paths. this is especially critical when dealing with ttl-level logic thresholds. ? keep the driver as close to the load as possible to minimize the length of high-current traces. this reduces the series induc tance to improve high- speed switching, while r educing the loop area that can radiate emi to the driver inputs and other surrounding circuitry. ? many high-speed power circuits can be susceptible to noise injected from t heir own output or other external sources, possibly causing output re- triggering. these effects can be especially obvious if the circuit is tested in breadboard or non-optimal circuit layouts with long input, enable, or output leads. for best results, make connections to all pins as short and direct as possible. ? the turn-on and turn-off current paths should be minimized as discussed in the following sections. figure 39 shows the pulsed gate-drive current path when the gate driver is suppl ying gate charge to turn the mosfet on. the current is supplied from the local bypass capacitor, c byp , and flows through the driver to the mosfet gate and to gr ound. to reach the high peak currents possible, the resistance and inductance in the path should be minimized. the localized c byp acts to contain the high peak-current pulses within this driver- mosfet circuit, preventing them from disturbing the sensitive analog circuitry in the pwm controller. pwm v ds v dd c byp fan3111 figure 39. current path for mosfet turn-on figure 40 shows the current path when the gate driver turns the mosfet off. idea lly, the driver shunts the current directly to the source of the mosfet in a small circuit loop. for fast turn -off times, the resistance and inductance in this path should be minimized. pwm v ds v dd c byp fan3111 figure 40. current path for mosfet turn-off
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan3111 ? rev. 1.0.2 14 fan3111 ? single 1a high-speed, low-side gate driver truth table of logic operation the fan3111 truth table indica tes the operational states using the dual-input configur ation. in a non-inverting driver configurati on, the in- pin should be a logic low signal. if the in- pin is connected to logic high, a disable function is realized, and the driver output remains low regardless of the stat e of the in+ pin. table 1. fan3111 truth table in+ in- out 0 0 0 0 1 0 1 0 1 1 1 0 in the non-inverting driver c onfiguration in figure 41, the in- pin is tied to ground and the input signal (pwm) is applied to the in+ pin. the in- pin can be connected to logic high to disable the dr iver and the output remains low, regardless of the state of the in+ pin. vdd gnd in- in+ out pwm fan3111 figure 41. dual-input driver enabled, non- inverting configuration in the inverting driver applic ation shown in figure 42, the in+ pin is tied high. pulling the in+ pin to gnd forces the output low, regardless of t he state of the in- pin. vdd gnd in- in+ out pwm fan3111 figure 42. dual-input driver enabled, inverting configuration thermal guidelines gate drivers used to switch mosfets and igbts at high frequencies can dissipate significant amounts of power. it is important to determine the driver power dissipation and the resulting j unction temperature in the application to ensure that t he part is operating within acceptable temperature limits. the total power dissipation in a gate driver is the sum of three components; p gate , p quiescent , and p dynamic : dynamic gate total p p p ? ? (1) gate driving loss: the most significant power loss results from supplying gate current (charge per unit time) to switch the load mosfet on and off at the switching frequency. the power dissipation that results from driving a mosfet at a specified gate-source voltage, v gs , with gate charge, q g , at switching frequency, f sw , is determined by: sw gs g gate f v q p ? ? ? (2) dynamic pre-drive / shoot-through current: a power loss resulting from internal current consumption under dynamic operating conditions, including pin pull-up / pull- down resistors, can be obtained using the graphs in figure 11 and figure 12 in typical performance characteristics to determine the current i dynamic drawn from v dd under actual operating conditions: dd dynamic dynamic v i p ? ? (3) once the power dissipated in the driver is determined, the driver junction temperature rise with respect to the device lead can be evaluated using thermal equation: c jl total j t p t ? ? ? (4) where: t j = driver junction temperature; jl = thermal resistance from junction to lead; and t l = lead temperature of device in application. the power dissipated in a gate-drive circuit is independent of the drive-circuit resistance and is split proportionately among the resistances present in the driver, any discrete series resistor present, and the gate resistance internal to the power switching mosfet. power dissipated in the driver may be estimated using the following equation: ? ? ? ? ? ? ? ? ? ? ? fet gate, ext driver out, driver out, total pkg r r r r p p (5) where: p pkg = power dissipated in the driver package; r out,driver = estimated driver impedance derived from i out vs. v out waveforms; r ext = external series resistance connected between the driver output and the gate of the mosfet; and r gate,fet = resistance internal to the load mosfet gate and source connections.
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan3111 ? rev. 1.0.2 15 fan3111 ? single 1a high-speed, low-side gate driver typical application diagrams logic pwm 33 ? 33 ? downstream converters rectified ac input fan3111 fan3111 v dd v dd q1b q1a figure 43. pfc boost circuit utilizing distributed drivers for parallel power switches q1a and q1b figure 44. driver for forward converter low-side switch v in q2 vsec d1 d2 q1 t1 v dd cc pwm 0.1f t2 fan3111 figure 45. driver for two-transistor, forward-converter gate transformer
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan3111 ? rev. 1.0.2 16 fan3111 ? single 1a high-speed, low-side gate driver table 2. related products part number type gate drive (10) (sink/src) input threshold logic package fan3111c single 1a +1.1a / -0.9a cmos single channel of dual-input/single-output sot23-5, mlp6 fan3111e single 1a +1.1a / -0.9a external (11) single non-inverting channel with external reference sot23-5, mlp6 FAN3100C single 2a +2.5a / -1.8a cmos single channel of two-input/one-output sot23-5, mlp6 fan3100t single 2a +2.5a / -1.8a ttl single c hannel of two-input/one-output sot23-5, mlp6 fan3226c dual 2a +2.4a / -1.6a cmos dual inverting channels + dual enable soic8, mlp8 fan3226t dual 2a +2.4a / -1.6a ttl dual in verting channels + dual enable soic8, mlp8 fan3227c dual 2a +2.4a / -1.6a cmos dual n on-inverting channels + dual enable soic8, mlp8 fan3227t dual 2a +2.4a / -1.6a ttl dual non- inverting channels + dual enable soic8, mlp8 fan3228c dual 2a +2.4a / -1.6a cmos dual channels of two-input/one-output, pin config.1 soic8, mlp8 fan3228t dual 2a +2.4a / -1.6a ttl dual channels of two-input/one-output, pin config.1 soic8, mlp8 fan3229c dual 2a +2.4a / -1.6a cmos dual channels of two-input/one-output, pin config.2 soic8, mlp8 fan3229t dual 2a +2.4a / -1.6a ttl dual channels of two-input/one-output, pin config.2 soic8, mlp8 fan3268t dual 2a +2.4a / -1.6a ttl 18v half-bridge driver: non-inverting channel (nmos) and inverting channel (pmos) + dual enables soic8 fan3223c dual 4a +4.3a / -2.8a cmos dual inverting channels + dual enable soic8, mlp8 fan3223t dual 4a +4.3a / -2.8a ttl dual in verting channels + dual enable soic8, mlp8 fan3224c dual 4a +4.3a / -2.8a cmos dual n on-inverting channels + dual enable soic8, mlp8 fan3224t dual 4a +4.3a / -2.8a ttl dual non- inverting channels + dual enable soic8, mlp8 fan3225c dual 4a +4.3a / -2.8a cmos dual channels of two-input/one-output soic8, mlp8 fan3225t dual 4a +4.3a / -2.8a ttl dual channels of two-input/one-output soic8, mlp8 fan3121c single 9a +9.7a / -7.1a cmos singl e inverting channel + enable soic8, mlp8 fan3121t single 9a +9.7a / -7.1a ttl singl e inverting channel + enable soic8, mlp8 fan3122t single 9a +9.7a / -7.1a cmos single non-inverting channel + enable soic8, mlp8 fan3122c single 9a +9.7a / -7.1a ttl single non-inverting channel + enable soic8, mlp8 notes: 10. typical currents with out at 6v and v dd = 12v. 11. thresholds proportional to an exte rnally supplied reference voltage.
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan3111 ? rev. 1.0.2 17 fan3111 ? single 1a high-speed, low-side gate driver physical dimensions 5 1 4 3 2 land pattern recommendation b a l c 0.10 c 0.20 cab 0.60 ref 0.55 0.35 seating plane 0.25 gage plane 8 0 notes: unless othewise specified a) this package conforms to jedec mo-178, issue b, variation aa, b) all dimensions are in millimeters. 1.45 max 1.30 0.90 0.15 0.05 1.90 0.95 0.50 0.30 3.00 2.60 1.70 1.50 3.00 2.80 symm c 0.95 0.95 2.60 0.70 1.00 see detail a 0.22 0.08 c) ma05brev5 top view (0.30) figure 46. 5-lead sot-23 package drawings are provided as a servic e to customers considering fairchild co mponents. drawings may change in any manner without notice. please note the revision and/or date on the drawi ng and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online pack aging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ .
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan3111 ? rev. 1.0.2 18 fan3111 ? single 1a high-speed, low-side gate driver

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